There are a number of conventional processes for packaging integrated circuit (IC) dice. By way of example, many IC packages utilize a metallic leadframe that has been stamped or etched from a metal sheet to provide electrical interconnects to external devices. The die may be electrically connected to the leadframe by means of bonding wires, solder bumps or other suitable electrical connections. In general, the die and portions of the leadframe are encapsulated with a molding material to protect the delicate electrical components on the active side of the die while leaving selected portions of the leadframe exposed to facilitate electrical connection to external devices.
The resultant IC packages are often mounted onto printed circuit boards (PCBs). The PCB is used to mechanically support and electrically connect electronic components including the IC package using conductive pathways, or traces, typically etched from copper sheets laminated onto a non-conductive substrate. In many applications, it is desirable to position various non-active (or passive) components along some of the traces to interrupt certain signal transmission paths between the die and an external device or power supply. By way of example, one or more of resistors, capacitors and/or inductors are often mounted onto the PCB. A bypass capacitor, for instance, is often used to decouple one part of the circuit from another. More specifically, a bypass capacitor may be used to bypass the power supply or other high impedance component of the circuit.
Building passive components of integrated circuits during wafer fabrication has limitations on performance due to the need for higher inductance, capacitance or resistance.
Direct contact of passive components on leads of conventional wire bond packages provide similar function as integrated passive components; however, there are disadvantages to this approach. These disadvantages include, but are not limited to, a larger foot print of the packaged devices in order to include the passive components on the leads, higher package cost due to the requirement of both passive attach, usually with a solder reflow process and additional wire bonds and finally longer electrical signal paths between integrated circuit die and the passive components which impacts energy loss.
With the evolution of mobile devices to become smaller in size, smaller foot prints of packaged devices is required.
As such, there has arisen a need for an improved packaging of the combination of integrated circuits and passive components.